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? semiconductor components industries, llc, 2001 november, 2001 rev. 1 1 publication order number: ncs7101/d ncs7101 1.8 volt rail-to-rail operational amplifier the ncs7101 operational amplifier provides railtorail operation on both the input and output. the output can swing within 50 mv of each rail. this railtorail operation enables the user to make full use of the entire supply voltage range available. it is designed to work at very low supply voltages (1.8 v and ground), yet can operate with a supply of up to 10 v and ground. the ncs7101 is available in the space saving sot235 package with two industry standard pinouts. features ? low voltage, single supply operation (1.8 v and ground to 10 v and ground) ? 1.0 pa input bias current ? unity gain bandwidth of 1.0 mhz at 5.0 v, 0.9 mhz at 1.8 v ? output voltage swings within 50 mv of both rails @ 1.8 v ? no phase reversal on the output for overdriven input signals ? input offset trimmed to 1.0 mv ? low supply current (i d = 1.0 ma) ? works down to two discharged nicd battery cells ? esd protected inputs up to 2.0 kv typical applications ? dual nicd/nimh cell powered systems ? portable communication devices ? low voltage active filters ? power supply monitor and control ? interface to dsp figure 1. typical application 1.8 v to 10 v this device contains 68 active transistors. - + rail to rail input rail to rail output device package shipping ordering information ncs7101sn1t1 sot235 (tsop5, sc595) 3000 units/ 7 tape & reel http://onsemi.com case 483 sot235 (tsop5, sc595) sn suffix pin connections 1 v out 1 2 3 4 5 v cc noninverting input 2 3 5 4 v ee inverting input style 1 pin out (sn1t1) low voltage railtorail operational amplifier + 1 v out v ee noninverting input 2 3 5 4 v cc inverting input style 2 pin out (sn2t1) + marking diagram 1 5 aaxyw x = c for sn1 d for sn2 y = year w = work week ncs7101sn2t1 sot235 (tsop5, sc595) 3000 units/ 7 tape & reel
ncs7101 http://onsemi.com 2 maximum ratings rating symbol value unit supply voltage (v cc to v ee ) v s 10 v input differential voltage range (note 1) v idr v ee 300 mv to 10 v v input common mode voltage range (note 1) v icr v ee 300 mv to 10 v v output short circuit duration (note 2) t sc indefinite sec junction temperature t j 150 c power dissipation and thermal characteristics sot235 package thermal resistance, junctiontoair power dissipation @ t a = 70 c r ja p d 220 364 c/w mw storage temperature range t stg 65 to 150 c esd protection at any pin human body model (note 3) v esd 2000 v 1. either or both inputs should not exceed the range of v ee 300 mv to v ee + 10 v. 2. maximum package power dissipation limits must be observed to ensure that the maximum junction temperature is not exceeded. t j = t a + (p d r ja ) 3. esd data available upon request. dc electrical characteristics (v cc = 2.5 v, v ee = 2.5 v, v cm = v o = 0, r l to gnd, t a = 25 c, unless otherwise noted.) characteristics symbol min typ max unit input offset voltage v cc = 0.9 v, v ee = 0.9 v t a = 25 c t a = 40 c to 85 c v cc = 2.5 v, v ee = 2.5 v t a = 25 c t a = 40 c to 85 c v cc = 5.0 v, v ee = 5.0 v t a = 25 c t a = 40 c to 85 c v io 7.0 9.0 7.0 9.0 7.0 9.0 0.6 0.6 0.6 7.0 9.0 7.0 9.0 7.0 9.0 mv input offset voltage temperature coefficient (r s = 50) t a = 40 c to 105 c d v io / d t 8.0 m v/ c input bias current (v cc = 1.8 v to 10 v) |i ib | 1.0 pa common mode input voltage range v icr v ee v cc v large signal voltage gain v cc = 5.0 v, v ee = 5.0 v r l = 10 k w r l = 2.0 k w a vol 16 16 50 30 kv/v output voltage swing, high (v id = 0.2 v) v cc = 0.9 v, v ee = 0.9 v (t a = 25 c) r l = 10 k r l = 2.0 k t a = 40 c to 85 c r l = 10 k r l = 2.0 k v cc = 2.5 v, v ee = 2.5 v (t a = 25 c) r l = 600 r l = 2.0 k t a = 40 c to 85 c r l = 600 r l = 2.0 k v cc = 5.0 v, v ee = 5.0 v (t a = 25 c) r l = 600 r l = 2.0 k t a = 40 c to 85 c r l = 600 r l = 2.0 k v oh 0.85 0.80 0.85 0.79 2.10 2.35 2.00 2.40 4.40 4.80 4.40 4.80 0.88 0.82 2.21 2.44 4.60 4.88 v
ncs7101 http://onsemi.com 3 dc electrical characteristics (continued) (v cc = 2.5 v, v ee = 2.5 v, v cm = v o = 0, r l to gnd, t a = 25 c, unless otherwise noted.) characteristics unit max typ min symbol output voltage swing, low (v id = 0.2 v) v cc = 0.9 v, v ee = 0.9 v (t a = 25 c) r l = 10 k r l = 2.0 k t a = 40 c to 85 c r l = 10 k r l = 2.0 k v cc = 2.5 v, v ee = 2.5 v (t a = 25 c) r l = 600 r l = 2.0 k t a = 40 c to 85 c r l = 600 r l = 2.0 k v cc = 5.0 v, v ee = 5.0 v (t a = 25 c) r l = 600 r l = 2.0 k t a = 40 c to 85 c r l = 600 r l = 2.0 k v ol 0.88 0.82 2.22 2.38 4.66 4.88 0.85 0.80 0.85 0.78 2.10 2.35 2.00 2.30 4.40 4.80 4.35 4.80 v common mode rejection ratio v in = 0 to 10 v v in = 0 to 5.0 v cmrr 65 60 db power supply rejection ratio v cc /v ee = 10 v/ground, v s = 2.5 v psrr 65 db output short circuit current (v in diff = 1.0 v) v cc = +0.9 v, v ee = 0.9 v source sink v cc = +2.5 v, v ee = 2.5 v source sink v cc = 5.0 v, v ee = 5.0 v source sink i sc 20 60 50 140 3.0 3.0 25 25 72 72 60 20 140 50 ma power supply current (v o = 0 v) v cc = +0.9 v, v ee = 0.9 v t a = 25 c t a = 40 c to 85 c v cc = +2.5 v, v ee = 2.5 v t a = 25 c t a = 40 c to 85 c v cc = 5.0 v, v ee = 5.0 v t a = 25 c t a = 40 c to 85 c i d 0.97 1.05 1.13 1.20 1.30 1.30 1.40 1.40 1.50 ma
ncs7101 http://onsemi.com 4 ac electrical characteristics (v cc = 2.5 v, v ee = 2.5 v, v cm = v o = 0, r l to gnd, t a = 25 c, unless otherwise noted.) characteristics symbol min typ max unit slew rate (v o = 2.0 to 2.0 v, r l = 2.0 k w , a v = 1.0) sr 0.7 1.2 3.0 v/ m s gain bandwidth product (v cc = 10 v) gbw 0.5 1.0 3.0 mhz gain margin (r l = 10 k, c l = 5.0 pf) am 6.5 db phase margin (r l = 10 k, c l = 5.0 pf) f m 60 deg power bandwidth (v o = 4.0 vpp, r l = 2.0 k w , thd 1.0%) bw p 130 khz total harmonic distortion (v o = 4.0 vpp, r l = 2.0 k w , a v = 1.0) f = 1.0 khz f = 10 khz thd 0.02 0.2 % differential input resistance (v cm = 0 v) r in 1.0 tera w differential input capacitance (v cm = 0 v) c in 2.0 pf equivalent input noise voltage (freq = 1.0 khz) e n 140 nv/ hz
ncs7101 http://onsemi.com 5 t, time (1.0 m s/div) t, time (500 ns/div) t a , ambient temperature ( c) figure 2. output saturation voltage versus load resistance figure 3. output saturation voltage versus load current figure 4. input bias current versus temperature figure 5. gain and phase versus frequency figure 6. transient response figure 7. slew rate 0 100 1.0 k 10 k 100 k 1.0 m r l , load resistance ( ) 400 800 1200 1200 800 400 0 high state output sourcing current low state output sinking current v s = 2.5 v r l = to gnd t a = 25 c 0 0 2.0 8.0 10 12 i l , load current (ma) 0.4 0.8 1.2 1.2 0.8 0.4 0 high state output sourcing current low state output sinking current v s = 2.5 v r l = to gnd t a = 25 c 4.0 6.0 v sat , output saturation voltage (v) i ib , input current (pa) 1000 10 0.1 0 0 25 50 75 100 125 1.0 v s = 2.5 v r l = c l = 0 a v = 1.0 500 mv/div 50 mv/div v ee v cc v sat , output saturation voltage (mv) v ee v cc 100 v s = 2.5 v v o = 4.0 v pp r l = 10 k c l = 10 pf a v = 1.0 t a = 25 c v s = 2.5 v v o = 4.0 v pp r l = 10 k c l = 10 pf a v = 1.0 t a = 25 c f, frequency (hz) a vol , gain (db) 100 60 20 0 10 100 40 v s = 5.0 v r l = 100 k t a = 25 c 80 1.0 1.0 k 10 k 100 k 1.0 m 10 m , excess phase ( ) 180 140 100 60 20 0 phase gain
ncs7101 http://onsemi.com 6 2.0 8.0 10 k 6.0 100 k 1.0 k 1.0 m 4.0 0 r l = 10 k a v = 1.0 t a = 25 c 14 figure 8. output voltage versus frequency v out , output voltage (v pp ) f, frequency (hz) 10 12 v s = 5.0 v v s = 2.5 v v s = 0.9 v figure 9. common mode rejection versus frequency figure 10. power supply rejection versus frequency f, frequency (hz) 10 100 1.0 k 10 k 10 m cmr, common mode rejection (db) 10 0 10 100 100 k 1.0 m 20 30 40 50 60 70 80 90 v s = 2.5 v r l = t a = 25 c a v = 1.0 f, frequency (hz) 10 100 1.0 k 10 k 10 m psr, power supply rejection (db) 10 0 10 100 100 k 1.0 m 20 30 40 50 60 70 80 90 v s = 2.5 v r l = t a = 25 c a v = 1.0 psr+ psr 0 v s , supply voltage (v) figure 11. output short circuit sinking current versus supply voltage |i sc | , output short circuit current (ma) 140 120 100 80 60 40 20 0 40 c 85 c 25 c output pulsed test at 3% duty cycle 1.0 2.0 3.0 4.0 5.0 figure 12. output short circuit sourcing current versus supply voltage 0 v s , supply voltage (v) |i sc | , output short circuit current (ma) 140 120 100 80 60 40 20 0 40 c 85 c 25 c output pulsed test at 3% duty cycle 1.0 2.0 3.0 4.0 5.0 v s , supply voltage (v) figure 13. supply current versus supply voltage with no load 0 1.0 2.0 3.0 4.0 5.0 r l = a v = 1.0 v in = 0 v |i d | , supply current (ma) 1.2 1.0 0.8 0.6 0.4 0.2 0 40 c 85 c 25 c 1.4
ncs7101 http://onsemi.com 7 3.0 50 25 0 25 50 75 100 2.0 1.0 0 125 t a , ambient temperature ( c) v s = 2.5 v r l = 10 k c l = 5.3 pf t a , ambient temperature ( c) 1.6 50 25 0 25 50 75 100 1.2 0.8 0.4 0 125 r l = 10 k c l = 10 pf a v = 1.0 t a = 25 c +slew rate, v s = 0.9 v slew rate, v s = 2.5 v slew rate, v s = 0.9 v 10 1.0 0.01 0.1 0.001 f, frequency (hz) 10 1.0 k 100 100 k 10 k v s = 2.5 v v out = 4.0 v pp r l = 10 k t a = 25 c figure 14. total harmonic distortion versus frequency with 5.0 v supply figure 15. total harmonic distortion versus frequency with 10 v supply figure 16. total harmonic distortion versus frequency with 5.0 v supply figure 17. total harmonic distortion versus frequency with 10 v supply f, frequency (hz) 0.01 0.001 0.1 1.0 10 10 1.0 k 100 100 k 10 k v s = 5.0 v v out = 8.0 v pp r l = 10 k t a = 25 c figure 18. slew rate versus temperature (avg.) figure 19. gain bandwidth product versus temperature +slew rate, v s = 2.5 v thd, total harmonic distortion (%) gbw, gain bandwidth product (mhz) sr, slew rate (v/ m s) a v = 1.0 a v = 10 a v = 100 a v = 1000 a v = 1.0 a v = 10 a v = 100 a v = 1000 a v = 1.0 a v = 10 a v = 100 a v = 1000 f, frequency (hz) 10 100 1.0 k 10 k 100 k thd, total harmonic distortion (%) 0.001 0.01 0.1 1.0 10 v s = 2.5 v v out = 4.0 v pp r l = 2 k t a = 25 c a v = 1.0 a v = 10 a v = 100 a v = 1000 f, frequency (hz) 10 100 1.0 k 10 k 100 k thd, total harmonic distortion (%) 0.001 0.01 0.1 1.0 10 v s = 5.0 v v out = 8.0 v pp r l = 2 k t a = 25 c thd, total harmonic distortion (%)
ncs7101 http://onsemi.com 8 figure 20. voltage gain and phase versus frequency 80 0 60 40 20 80 0 60 40 20 phase margin gain margin 50 25 0 25 50 75 100 125 v s = 2.5 v r l = 10 k c l = 10 pf t a , ambient temperature ( c) figure 21. gain and phase margin versus temperature a m , gain margin (db) f m , phase margin ( ) 70 50 30 10 70 50 30 10 f m , phase margin ( ) 10 100 1.0 k 1.0m phase margin gain margin 10 k 40 20 0 20 40 80 60 100 v s = 2.5 v r l = 10 k c l = 5.0 pf t a = 25 c 40 20 0 20 40 80 60 100 r t , differential source resistance ( w ) figure 22. gain and phase margin versus differential source resistance a m , gain margin (db) 100 k figure 23. gain and phase margin versus output load capacitance figure 24. output voltage swing versus supply voltage 0 2.0 v cc v ee , supply voltage (v) 8.0 0 6.0 4.0 2.0 r l = 10 k a v = 100 t a = 25 c split supplies v out , output voltage (v pp ) 4.0 6.0 8.0 10 10 12 30 30 10 10 300 60 140 220 10 k 100 k 1.0 m 10 m 100 m f, frequency (hz) a v , gain (db) 40 20 0 20 20 100 180 260 50 20 f , excess phase ( ) f m , phase margin ( ) 1.0 10 1000 phase margin gain margin 100 20 40 70 60 v s = 2.5 v r l = 10 k a v = 100 t a = 25 c 0 10 20 30 40 60 50 70 c l , capacitive load (pf) a v , gain margin (db) 50 30 0 10 r l = 10 k a v = 100 t a = 25 c v s = 0.9 v v s = 2.5 v figure 25. gain and phase margin versus supply voltage 40 2.0 1.0 60 80 0 70 3.0 4.0 5.0 v s , supply voltage (v) a m , gain margin (db) a v = 100 r l = 10 k c l = 0 t a = 25 c phase margin gain margin 50 30 10 20 0
ncs7101 http://onsemi.com 9 90 v s , supply voltage (v) 2.0 4.0 3.0 1.0 5.0 0 70 100 60 80 110 120 r l = 10 k c l = 0 t a = 25 c figure 26. open loop voltage gain versus supply voltage (split supplies) a vol , open loop gain (db) figure 27. input offset voltage versus common mode input voltage range, v s = 2.5 v 0 3.0 1.0 2.0 15 5 20 10 10 20 15 5 0 1.0 2.0 3.0 v cm , common voltage range (v) v io , input offset voltage (mv) v s = 2.5 v r l = c l = 0 a v = 1.0 t a = 25 c figure 28. input offset voltage versus common mode input voltage range, v s = 0.9 v 0 0.6 0.2 0.4 10 20 15 0 0.2 0.4 1.0 v cm , common mode input voltage (v) v io , input offset voltage (mv) v s = 0.9 v r l = c l = 0 a v = 1.0 t a = 25 c 0.8 1.0 0.6 0.8 5 20 15 10 5 figure 29. commonmode input voltage range versus power supply voltage 0 2.0 6.0 4.0 3.0 4.0 v s , supply voltage (v) v cm , common mode input voltage range (v) v io = 5.0 mv r l = c l = 0 a v = 1.0 t a = 25 c 1.0 0.5 5.0 2.0 6.0 4.0 2.0
ncs7101 http://onsemi.com 10 application information and operating description general information the ncs7101 is a railtorail input, railtorail output operational amplifier that features guaranteed 1.8 volt operation. this feature is achieved with the use of a modified analog cmos process that allows the implementation of depletion mosfet devices. the amplifier has a 1.0 mhz gain bandwidth product, 1.2 v/ m s slew rate and is operational over a power supply range less than 1.8 v to as high as 10 v. inputs the input topology of this device series is unconventional when compared to most low voltage operational amplifiers. it consists of an nchannel depletion mode differential transistor pair that drives a folded cascode stage and current mirror. this configuration extends the input common mode voltage range to encompass the v ee and v cc power supply rails, even when powered from a combined total of less than 1.8 volts. figures 27 and 28 show the input common mode voltage range versus power supply voltage. the differential input stage is laser trimmed in order to minimize offset voltage. the nchannel depletion mode mosfet input stage exhibits an extremely low input bias current of less than 40 pa. the input bias current versus temperature is shown in figure 4. either one or both inputs can be biased as low as v ee minus 300 mv to as high as 10 v without causing damage to the device. if the input common mode voltage range is exceeded, the output will not display a phase reversal but it may latch in the appropriate high or low state. the device can then be reset by removing and reapplying power. if the maximum input positive or negative voltage ratings are to be exceeded, a series resistor must be used to limit the input current to less than 2.0 ma. the ultra low input bias current of the ncs7101 allows the use of extremely high value source and feedback resistor without reducing the amplifier's gain accuracy. these high value resistors, in conjunction with the device input and printed circuit board parasitic capacitances c in , will add an additional pole to the single pole amplifier shown in figure 30. if low enough in frequency, this additional pole can reduce the phase margin and significantly increase the output settling time. the effects of c in , can be canceled by placing a zero into the feedback loop. this is accomplished with the addition of capacitor c fb . an approximate value for c fb can be calculated by: c fb r in c in r fb figure 30. input capacitance pole cancellation + - output r fb c in r in c fb c in = input and printed circuit board capacitance input output the output stage consists of complimentary p and n channel devices connected to provide railtorail output drive. w ith a 2.0 k load, the output can swing within 100 mv of either rail. it is also capable of supplying over 95 ma when powered from 10 v and 3.0 ma when powered from 1.8 v. when connected as a unity gain follower, the ncs7101 can directly drive capacitive loads in excess of 390 pf at room temperature without oscillating but with significantly reduced phase margin. the unity gain follower configuration exhibits the highest bandwidth and is most prone to oscillations when driving a high value capacitive load. the capacitive load in combination with the amplifier's output impedance, creates a phase lag that can result in an underdamped pulse response or a continuous oscillation. figure 32 shows the effect of driving a large capacitive load in a voltage follower type of setup. when driving capacitive loads exceeding 390 pf, it is recommended to place a low value isolation resistor between the output of the op amp and the load, as shown in figure 31. the series resistor isolates the capacitive load from the output and enhances the phase margin. refer to figure 33. larger values of r will result in a cleaner output waveform but excessively large values will degrade the large signal rise and fall time and reduce the output's amplitude. depending upon the capacitor characteristics, the isolation resistor value will typically be between 50 to 500 ohms. the output drive capability for resistive and capacitive loads is shown in figures 2, 3, and 23. figure 31. capacitance load isolation + - output r isolation resistor r = 50 to 500 c l input note that the lowest phase margin is observed at cold temperature and low supply voltage.
ncs7101 http://onsemi.com 11 figure 32. small signal transient response with large capacitive load figure 33. small signal transient response with large capacitive load and isolation resistor.
ncs7101 http://onsemi.com 12 the noninverting input threshold levels are set so that the capacitor voltage oscillates between 1/3 and 2/3 of v cc . this requires the resistors r 1a , r 1b and r 2 to be of equal value. the following formula can be used to approximate the output frequency. r t 470 k r 2 470 k r 1b 470 k r 1a 470 k c t 1.0 nf v cc f o = 1.5 khz 0.67 v cc - + 0.9 v f o 1 1.39 r t c t v cc 0.33 v cc 0 output voltage timing capacitor voltage figure 34. square wave oscillator r 1b 470 k v cc d 2 1n4148 f o - + v cc r 2 470 k d 1 1n4148 10 k 10 k 1.0 m cw r 1a 470 k c t 1.0 nf 0.67 v cc v cc 0.33 v cc 0 output voltage timing capacitor voltage 0.67 v cc v cc 0.33 v cc 0 output voltage timing capacitor voltage the timing capacitor c t will charge through diode d 2 and discharge through diode d 1 , allowing a variable duty cycle. the pulse width of the signal can be programmed by adjusting the value of the trimpot. the ca- pacitor voltage will oscillate between 1/3 and 2/3 of v cc , since all the resistors at the noninverting input are of equal value. clockwise, low duty cycle counterclockwise, high duty cycle figure 35. variable duty cycle pulse generator cww r 1 1.0 m r 2 1.0 m r 3 1.0 k c in 10 f 2.5 v 10,000 m f + - c eff. r 1 r 3 c in 2.5 v figure 36. positive capacitance multiplier
ncs7101 http://onsemi.com 13 f l 1 2 r 1 c 1 200 hz f h 1 2 r f c f 4.0 khz a f 1 r f r 2 11 a f f l f h r 1 10 k r f 100 k r 2 10 k c f 400 pf 0.9 v 0.9 v c 1 80 nf v o + - v in figure 37. voice band filter r sense v cc + - v supply v in i sink v in r sense figure 38. high compliance current sink i s v o 1.00 a 67.93 mv 0.50 a 78.67 mv 3.3 k r 3 1.0 k r l i s 5.0 v r 4 2.4 k v l for best performance, use low tolerance resistors. + - 1.0 r sense r 5 1.0 k r 1 1.0 k figure 39. high side current sense r 2 v o
ncs7101 http://onsemi.com 14 k r 2 r 2 v cc + - i l v s r 1 figure 40. current source k r 1 r 1 , note that i l is independent of r l v o r l v s i l r 1 v cc + - figure 41. current to voltage converter v o = i s r 1 v o i s r 1 v cc + - figure 42. voltage to current converter v o i r1 i l v r1 r 1 v s r 1 r l i r1 i l v s i = 0
ncs7101 http://onsemi.com 15 r 2 v cc + - v o v 2 r 4 r 3 r 4
r 2 r 1 1
v 1 r 2 r 1 figure 43. differential amplifier r 1 r 3 v o r 4 v 2 v 1 if r 1 = r 3 , and r 2 = r 4 , the equation simplifies to: v o (v 2 v 1 ) r 2 r 1 r 4 v cc + - v o r 2 v 1 r 1 v 2 r 2 v 3 r 3
figure 44. summing amplifier r 2 r 3 v o r 5 v 2 v 1 to minimize input offset current take: r 5 = r 1 // r 2 // r 3 // r 4 r 1 v 2
ncs7101 http://onsemi.com 16 package dimensions sot235 (tsop5, sc595) case 48301 issue b notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. maximum lead thickness includes lead finish thickness. minimum lead thickness is the minimum thickness of base material. dim min max min max inches millimeters a 2.90 3.10 0.1142 0.1220 b 1.30 1.70 0.0512 0.0669 c 0.90 1.10 0.0354 0.0433 d 0.25 0.50 0.0098 0.0197 g 0.85 1.05 0.0335 0.0413 h 0.013 0.100 0.0005 0.0040 j 0.10 0.26 0.0040 0.0102 k 0.20 0.60 0.0079 0.0236 l 1.25 1.55 0.0493 0.0610 m 0 10 0 10 s 2.50 3.00 0.0985 0.1181 0.05 (0.002) 123 54 s a g l b d h c k m j on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. ncs7101/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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